A Compact Analytical Model for the Drain Current of Gate-All-Around Nanowire Tunnel FET Accurate From Sub-Threshold to ON-Stateby Rajat Vishnoi, Mamidala Jagadesh Kumar

IEEE Transactions on Nanotechnology

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Year
2015
DOI
10.1109/tnano.2015.2395879
Subject
Electrical and Electronic Engineering / Computer Science Applications

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1536-125X (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TNANO.2015.2395879, IEEE Transactions on Nanotechnology > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 

Abstract— We present a compact analytical model for the drain current of a Gate-All-Around (GAA) Nanowire Tunneling

Field Effect Transistor (TFET). The model takes into account the effect of oxide thickness, body doping, drain voltage and gate metal work function. The model uses a tangent line approximation method to integrate the tunneling generation rate in the source-body depletion region. The accuracy of the model is tested against three dimensional numerical simulations calibrated using experimental results. The model predicts the drain current accurately in both the ON-state (strong inversion) as well as in the sub-threshold region.

Index Terms— Tunneling Field Effect Transistor (TFET),

Nanowire, Three dimensional (3D) modeling, Sub-threshold slope (SS), ON-state current, OFF-state current.

I. INTRODUCTION

TFETs have been widely studied as an alternative to the

MOSFETs in the sub-100 nm regime [1-6] as they provide a better immunity to short channel effects (SCEs) and a lower sub-threshold swing (SS) [7]. The OFF-state leakage current in TFETs is low making them desirable in low power applications. A Gate-All-Around (GAA) structure, due to an enhanced electrostatic control of the gate over the channel, further improves SCEs and SS [8, 9]. Besides, the device geometry provides a higher ON-state current (ION) per unit area than planar devices. Hence, developing accurate models for the drain current of a GAA TFET becomes important.

A few analytical models have been developed for GAA

TFETs [10-11]. However, these models have limited accuracy in the sub-threshold region as they consider constant electric field (either peak or average value) in the entire tunneling region. Hence, it becomes important to develop a compact analytical model for the drain current of a GAA TFET accurate in the entire range of operating voltages.

In this work, we develop a compact analytical model for the drain current of a GAA nanowire TFET. Using the surface potential model from [12] to find the electric field in the tunneling region, we estimate the tunneling generation rate in the channel using the Kane’s model for band-to-band tunneling [13]. We then use the tangent line approximation

The authors are with the Department of Electrical Engineering, IIT Delhi,

New Delhi 110 016, India (e-mail: vishnoir@gmail.com; mamidala@ee.iitd.ac.in).

Fig. 1 Schematic view of the p-channel GAA nanowire TFET. method to integrate the tunneling generation rate along the channel, giving us the drain current.

The validity of the model is tested against 3D numerical simulations [14] calibrated against previously published experimental results [11].

II. MODEL DERIVATION

Fig. 1 shows the schematic view of the p-channel GAA nanowire TFET. It has the following parameters: channel length (L) = 50 nm, body doping (NS) = 1015/cm3, source/drain doping = 1021/cm3, length of source/drain regions = 50 nm, oxide thickness (Tox) = 2 nm, radius of the nanowire (TSi) = 10 nm and gate work-function (Φ) = 5.0 eV. [11]

The band diagram of the GAA TFET is shown in Fig. 2. We can observe that due to the thinning of the barrier between the valence and the conduction band, the carriers (holes in this case) can tunnel from the conduction band in the source to the valence band in the drain giving rise to the drain current (depicted by solid arrow). The tunneling generation rate ( btbG ) of carriers for band-to-band tunneling is given by the

Kane’s model [13]: ]exp[ 2/3

E

E

B

E

E

AG g g btb   (1) where A and B are tunneling parameters, E is the electric field and gE is the band gap of the material. We need to find the electric field E to estimate btbG . The factor  is the preexponential factor which is 2 for direct band-gap tunneling and 2.5 for indirect band-gap tunneling [13]. Since, our device material is silicon, which is an indirect band gap material, we have taken 5.2 .

A Compact Analytical Model for the Drain

Current of Gate All Around Nanowire Tunnel

FET accurate from Sub-threshold to ON-state

Rajat Vishnoi, Student Member, IEEE and Mamidala Jagadesh Kumar, Senior Member, IEEE

Copyright © 2015 IEEE. Personal use of this material is permitted. However, permission to use this material for any other other purposes must be obtained from the IEEE by sending a request to pubs-permissions@ieee.org . 1536-125X (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TNANO.2015.2395879, IEEE Transactions on Nanotechnology > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 2

Fig. 2 Band diagram of the GAA nanowire TFET at VGS = -1.5 V and VDS = 0.5 V showing the tunneling region R1 (solid arrow).

The surface potential in region R1 for a GAA TFET, derived in our previous work [12], can be written as:

Si dS

G d t

S

LqN

L

Lz

Cz   2 )cosh()(    (2a) 2/)( 2

Si dS

GC

LqN

C    (2b) )2/()1ln( 2 oxSi

Si ox

Sid

T

T

TL  (2c) where SN is the body doping and G is the electrostatic potential of the gate which is equal to FBGS VV  . Here FBV is the flat-band voltage of the TFET. dL is the characteristic length, tL is the length of the tunneling region (i.e. region R1) and C is the surface potential in region R2 and can be evaluated as given in [12]. By differentiating the surface potential (2), the electric field can be written as: z z zE S    )( )(  (3a) )sinh()( d t d L